1. Field
The present invention relates to a ferroelectric memory device.
2. Description of the Related Art
Next generation nonvolatile memories have been developed which can perform high speed rewriting operations as compared with the known EEPROMs or flash memories, have characteristics that enable great number of rewriting equal to or more than a 5 digit number, and aims at capacitance, speed, and cost equal to that of DRAMs. As next generation nonvolatile memories, there are FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), and the like. FeRAM which is a ferroelectric memory is provided with memory cells including ferroelectric capacitors and memory transistors (see JP-A-2006-134529).
In FeRAM described in JP-A-2006-134529 or the like, information is written in advance in the memory cells, and memory cell arrays are provided with ferroelectric memory fuses (also, referred to as ferro fuses) using the memory cells as fuses by reading the information when the power is switched on.
When the ferroelectric memory fuses share a main memory area and a bit line, bit line capacitance is increases. In this case, there is a difference in bit line capacitance between bit lines that are connected to the ferroelectric memory fuses and bit lines that are not connected to the ferroelectric memory fuses, and thus there is a disadvantage in that the reading margin of cells is reduced. When the capacitance of the bit lines that are not connected to the ferroelectric memory fuses increases to the same value of the capacitance of bit lines that are connected to the ferroelectric memory fuses, there is a disadvantage in that the chip area is drastically increased.
When the ferroelectric memory fuses are independent from the main memory area and have bit lines or sense amplifiers, the bit line capacitance of the main memory area can be made to be uniform. However, when bit lines, sense amplifiers, and a control circuit such as a column decoder are added, there is a disadvantage in that the chip area is drastically increased.